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Design Verification Engineer
Ref No.: 17-13315
Location: Santa Clara, California
Responsibilities will include developing the verification environment; developing test plans and verifying the function of the ASIC/FPGA at both the full chip and block level.

Minimally, we are looking for someone with
1. Min 7+ years of DV experience, with several complete and successful FPGA design/verification cycles under his/her belt
2. Strong SystemVerilog/UVM, C/C++ and scripting skills
The following is highly desirable -
3. Networking expert
4. HBM2, DDR4 memory experience
5. Experience with security protocols like MACSec, IPSec