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Reference # : 18-02303 Title : Wafersort Engineer
Location : California, CA
Experience Level : Start Date : 01/12/2018  
Description
 
Job Description (Posting).

 
 
Title: 
Wafersort Engineer

 
Need USC/GC only
 
 
 
JD:
 
 
 
·         
Skill Set- Verigy93K, Advantest, Scan Chain, Digital BIST, Pattern 
conversion.

 
·         
Multisite testing, Site to site correlation, Bench to Wafer 
correlation.

 
·         
Class Test Wafer Test, Final Package Test & HVM statistical data 
analysis.

 
·         
All IC's are High speed Analog IC's with limited digital interface. 
Engineering to HVM is expected for all IC's. Auto sort, multisite.

 
·         
Statistical Yield Analysis of Sort data thorough understanding of 
Various Sort Testers like Advantest, Eagle, etc.. Shall be mastered in Advantest 
Verigy93K

 
·         
Expertise in C++, automation scripting
 
·         
Should have gone through full cycle of Wafer sort/Package sort from 
Engineering testing through Final HVM transfer

 
·         
Expertise in using test equipment's like DSO, Sampling scopes, BERT, 
logic analyser, mustimeters, power supplies etc

 
·         
PVT characterization @ wafersort
 
 
 
 
 
Mandate 
Skills:

 
 
 
·         
Verigy93K
 
·         
VTRAN
 
·         
Sedana – Yield Analysis
 
·         
Galaxyian – Yield Analysis
 
·         
C++
 
·         
Wafersort
 
·         
Perl/Python scripting
Experience 7-9 Years
Qualification BE/B.Tech (Hons)
Skill (Primary) Technical Skills (ERS)-HW Board-Board bringup & debug
Job Family Engineering (Engg - Hardware & VLSI)
Band TP
Job Technical Lead - Hardware & VLSI
Requisition Source Skill on Tap
Removal Date 07-Nov-2018