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Design Verification Engineer (642167)
Ref No.: 18-08069
Location: Santa Clara, California
Start Date: 08/06/2018
Description:
Responsibilities (depends on the detailed assignment, the candidate may actually carry out a portion of the responsibilities below):
 Design the verification architecture of a high-end 64 bit super scalar micro-processor
 Draft and review the test scheme and test plan;
 Responsible for feature verification for a CPU block;
 Work with a team of DV engineers in development of all test cases, checkers, assertions, and test bench architecture;
Qualifications
 Minimum 5 years of design verification experience in micro-processor design, with programming ability in C, C++, System Verilog, UVM
 Knowledge in Core-CPU verification. Preference for experience in Load Store Unit, Data Cache Unit, Level 2 Cache, CPU L1-L2 Memory Subsystem interaction
 Must be a highly organized, detail-oriented self-starter, who works well independently, as well as in a team environment.
 Master’s degree preferred.
 Good verbal and written communication skills.

Candidate Details:Taleo 9780
Grade 15
Target Bill Rate: 63.70 or most competitive bill rate possible