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ASIC - RTL Design Engineer
Ref No.: 18-01596
Location: San Jose, California
Job Function:
  • Micro-architecture definition, RTL implementation, synthesis, timing analysis and post-silicon verification support.
  • Working with system engineer to understand wireless standards and define micro-architecture and perform bit-exact simulation.
  • Working with the physical design engineer to deliver netlist, spec timing constraints, perform timing analysis, and timing sign-off.

  • BS with extensive industry experience or MS is preferred.
  • Minimum of 5-10 years' experience in RTL Design
  • Strong knowledge with ASIC Frontend Tools & Implementation: Simulation, Waveform debugging tool, Linting, Formal Logic equivalence, Logic synthesis, STA, CDC checks
  • Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure