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Design for Test (DFT) Engineer
Ref No.: 18-01322
Location: San Diego, California
Start Date: 08/27/2018
 5 years' experience with the following:
 
  • ATPG (stuck, transition delay, bridge) with Synopsys Tetramax/Mentor TestKompress
  • ATPG pattern generation, coverage analysis and ATPG simulation. Ability to debug ATPG simulation failures is a plus.
  • DFT insertion using DFT Compiler
  • Good TCL and PERL scripting skills
  • MBIST insertion using Mentor Tessent, including memory repair. Ability to run and debug
  • MBIST simulations.