Previous Job
Design Verification
Ref No.: 18-01246
Location: Austin, Texas
Start Date / End Date: 08/13/2018 to 08/16/2019
  • Experienced with verification methodology UVM is a must.
  • Understand Fabric interconnect with ACE-VIP protocols.
  • Test-bench as SOC environment to work at top level using system verilog.
  • Develop test benches and tests, understanding sequencers/sequences, drivers, checkers, and monitors in a UVM environment.
  • Solid understanding of Computer Architecture.
  • Familiarity with ARM assembly along with debugging tarmac files is needed
  • Arm architecture knowledge is desired.
  • CPU architecture experience is desired.
  • Cache coherency with AMBA protocol is desired.
  • C/assembly tests debug with co-simulation with CPU cores is desired.
  • Experienced with verification methodology such UVM/VMM/OVM. UVM is required.
  • BSEE, preferably MSEE or PhD. At least 5 years of industry experience, 3 of which in a design verification role.
  • Proficient in System Verilog, UVM C++, Python/Perl is a plus.
  • Excellent verbal and written communication skills.