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Layout Design Engineer
Ref No.: 18-01070
Location: San Jose, California
Experience Level: 8 Years
Start Date: 07/16/2018
 Job Summary
 
In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products, on advanced CMOS processes.
 
Key Qualifications
The ideal candidate will have the following qualifications
  1. 5+ years experience in custom RF/analog layout with extensive knowledge on deep sub-micron CMOS (28nm, FINFET's, etc.)
  2. Knowledgeable on layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing
  3. Must recognize failure prone circuit and layout structures, proactively work with circuit designer for best approach to problems
  4. High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc.
  5. Familiarity of CADENCE layout tools and Mentor Graphics verification tools.
  6. Excellent communication skills and able to work with cross-functional teams
 
Detailed Description
As an RF layout designer, you will be responsible for
  • Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, Client/DAC, baseband filters, and bandgap/bias/LDO.
  • Layout of sensitive analog components including resistors, capacitors, and inductors
  • Block level and top-level layout through full verification flow including RLC extraction, DRC, LVS, and DFM checking
  • Co-work with designers on block level and top-level floor-planning
  • Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling
  • Top-level layout integration and verification, schedule management.