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ASIC Design Verification
Ref No.: 18-01060
Location: San Diego/San Jose, California
Position Type:Contract
Start Date / End Date: 06/04/2018 to 01/04/2019
Our team is hiring few ASIC DV (design verification) engineer, preferred in San Diego candidates first , but San Jose also considered.
Job Function:
  • Define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals.
  • Define overall verification strategies, methodologies, and simulation environment
  • Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications. Develop, maintain and publish verification specifications.
  • Analyze and debug simulation failures
  • Generates code coverage and functional coverage report
  • Run gate level simulation and debug them.
  • Perform the constraint assertion based verification
  • Minimum of 3-14 year experience in ASIC Verification.
  • Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti
  • Fluent in verification language such as UVM/OVM/RVM/System Verilog, Vera, Verilog
  • Experience in writing Test-plans and creating directed and random test cases
  • Strong scripting skills in Perl, Python, shell etc.
  • Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure
  • B.S. with extensive industry experience