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Emulation Engineer
Ref No.: 18-00994
Location: San Jose, California
Position Type:Contract
Experience Level: 11 Years
Start Date: 06/29/2018
 Description
  • Direct hands-on developing test benches for GPU/ large SoC Design.  
  • Writing and maintaining Complex Test Bench, using Verilog, System-Verilog, UVM, or SystemC
 
Requirements
  • 10+ years' experience, and direct hands-on developing test-benches with large SOC designs
  • Hands-on, with EDA vendor tools to include one of these Synopsys, Cadence and/or Mentor Graphics
  • Writing and maintaining Complex Test Bench, using Verilog, System-Verilog, UVM, or SystemC
  • Demonstrated Strong Python skills, 5+ years
  • Demonstrated Strong C/C++ skills, 5+ years
  • Defining Requirements, Architecting, Building, Testing and Maintaining, high volume testing frameworks and IT integration
  • Group Skills; Leadership on some tasks, and individual contributor on other tasks.
  • Ability to document your designs and the work of others as needed.