ASIC - RTL Design Engineer
Previous Job
ASIC - RTL Design Engineer
Ref No.: 18-00756
Location: San Diego, California
Position Type:Contract
Start Date: 05/15/2018
Job Function:
• Micro-architecture definition, RTL implementation, synthesis, timing analysis and post-silicon verification support.
• Working with system engineer to understand wireless standards and define micro-architecture and perform bit-exact simulation.
• Working with the physical design engineer to deliver netlist, spec timing constraints, perform timing analysis, and timing sign-off.

• BS with extensive industry experience or MS is preferred. • Minimum of 5-10 years' experience in RTL Design • Strong knowledge with ASIC Frontend Tools & Implementation: Simulation, Waveform debugging tool, Linting, Formal Logic equivalence, Logic synthesis, STA, CDC checks • Strong problem-solving skill to quickly identify and provide solution under tight schedule pressure