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Design Verification
Ref No.: 18-00459
Location: Austin, Texas
Experience Level: 7 Years
Start Date: 03/23/2018
Responsibilities Include:

• Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
• Familiarity with ARM assembly along with debugging tarmac files is valuable.
• Cache coherency with AMBA protocol is desired.
• C/assembly tests debug with co-simulation with CPU cores is desired.
• Arm architecture knowledge is desired but not needed.
• Enhance test benches and tests to achieve coverage goals.
• Support unit and super-unit debug on simulation and/or emulation platforms.

Experience Requirements:
• Experienced with verification methodology such UVM/VMM/OVM. UVM is preferred.
• Developed test plans of complex systems containing multiple state machines and protocol rules.
• Composed functional coverage assertions, preferably using system Verilog. The qualified candidate will possess the following:
• BSEE, preferably MSEE or PhD.
• At least 7 years of industry experience, 5 of which in a design verification role.
• Proficient in System Verilog,
• C++, Python/Perl is a plus.
• Excellent verbal and written communication skills.