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Design Verification
Ref No.: 18-00459
Location: Austin, Texas
Experience Level: 7 Years
Start Date: 03/23/2018
Description
 
•            Develop test plans, test benches and tests, creating sequences, drivers, checkers, and monitors in a UVM environment.
•            Root cause regression failures by debugging Tests/Sequences, RTL and C/Assembly co-simulation logs.
•            Develop tests/templates to run at mini-soc level and root cause fails.
•            Develop Unit Level and/or Cluster Level Test plans, Coverage Plans
•            Maintain regression failures by debugging tests/sequences, RTL.
•            Support debug of Unit RTL/Checkers at higher levels of integration such as Cluster/Top.
•            Enhance test benches and tests to achieve coverage goals.
•            Support unit and super-unit debug on simulation and/or emulation platforms.
•            Work closely with Architects and Logic Designers.
•            Drive Code and Functional Coverage closure.
•            Composed functional coverage assertions, preferably using system Verilog.
 
Requirements
  • Solid understanding of Computer Architecture.
  • Familiarity with ARM assembly along with debugging tarmac files is needed
  • Arm architecture knowledge is desired.
  • CPU architecture experience is desired.
  • Cache coherency with AMBA protocol is desired.
  • C/assembly tests debug with co-simulation with CPU cores is desired.
  • Experienced with verification methodology such UVM/VMM/OVM. UVM is required. BSEE, preferably MSEE or PhD. At least 5 years of industry experience, 3 of which in a design verification role. Proficient in System Verilog, UVM C++, Python/Perl is a plus. Excellent verbal and written communication skills.