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Design Verification Engineer
Ref No.: 17-01434
Location: San Diego, California
Start Date / End Date: 12/11/2017 to 06/15/2018
Job Function:

• Developing of test benches in UVM methodologies

• Calling c model function using DPI from test bench

• Developing random test bench

• Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.

• Develop, maintain and publish verification specifications

• Analyze and debug simulation failures

• Generates code coverage and functional coverage report
• Run gate level simulation and debug them

• Developing scripts for simulation and regression flow


• Minimum of 8+ years' experience in Verification with a leading chipset company is a primary requirement

• Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators like Incisive and VCS, and waveform viewer like Verdi

• Fluent in verification methodologies such as UVM, HVL languages such as System Verilog,

• Knowledge of OOP is required

• Knowledge of perl or python is must

• Strong problem solving skill to quickly identify

Work location : San Diego

Address: San Diego Directors Pl, 92121