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Digital Design Engineers for Mixed Signal ASICs.
Ref No.: 18-27610
Location: San Diego, California
Position Type:Contract
Experience Level: 5 Years
Start Date / End Date: 05/10/2018 to 08/10/2018
Job Title: Digital Design Engineers for Mixed Signal ASICs.
Job ID: 1964073
Duration: 12+ Months (strong possibility of further extension)
Location: San Diego, CA
Job Description:
Responsibilities include: Digital design and analog/mixed signal design support for PLL, DAC, ADC and other mixed-signal designs. Digital design aspects include full behavioral level description with high level synthesis languages and gate level synthesis, logic level synthesis, timing closure, power and signal integrity analysis and testability. Analog/mixed-signal support includes behavioral modeling of RF and analog blocks using Verilog in the cadence AMS environment and analog/digital integration and verification methodologies using Cadence AMS. Work in a dynamic team environment with aggressive schedule, chip power consumption and area targets.
Minimum Qualifications:
Bachelor’s degree in Electrical Engineering or Computer Engineering and 5 years of relevant experience with the following: - Digital ASIC design including architecture - RTL design for control and datapath, linting, synthesis, STA, and DFT - Experience with leading-edge ASIC development tools from Synopsys, Mentor, or Cadence
Preferred Qualifications:
- Master’s degree in Electrical Engineering or Computer Engineering - Experience designing mixed signal interfaces and integrating digital modules into mixed-signal ASICs
Required: Bachelor's, Electrical Engineering Preferred: Master's or equivalent experience
Rakesh Joshi
Team Lead - Recruitment

Description: cid:image001.jpg@01D3DC8E.67287DD0
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