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SOC Design Verification Engineer
Ref No.: 18-17368
Location: San Diego, California
Position Type:Contract
Experience Level: 10 Years
Start Date / End Date: 03/23/2018 to 06/23/2018
Job Title: SOC Design Verification Engineer
Job ID: 1963280
Location: San Jose, CA and San Diego, CA
Duration: 6+ Months contract
 
DESCRIPTION:
As a design verification engineer you will work with a fast paced Integrated Wireless Technology (IEEE 802.11x, BT, and FM) team with various wireless technologies, embedded into an ARM based SOC infrastructure. You will be responsible for building functional verification infrastructure, understanding the expected design functionality, developing test-plans as well as guiding the functional verification of complex SoCs by deploying UVM until coverage goals are achieved in order to insure the continued commercial success of our high quality products. You will have a great opportunity to work on cutting edge digital chipsets, leverage your pre and post silicon debug expertise, and develop the industrys best-in-class SOC verification methodologies.
Responsibilities:
As verification is a rapidly changing field and consumes the majority of the design process, developing and deploying new verification methodologies is an essential part of the work you will do. Assertions, simulation, formal verification, HW-SW co-verification and constraint/HVL-based verification are all tools in our verification toolbox you will use on a daily basis. You will be responsible for building functional verification infrastructure, understanding the expected design functionality, developing test-plans as well as guiding the functional verification of complex SoCs by deploying UVM until coverage goals are achieved in order to insure the continued commercial success of our high quality products.
Minimum Qualifications:
7 to 10 years of directly related industry experience in ASIC / SoC Verification
Expert knowledge in UVM, which is an object-oriented Hardware verification language library based on Sytem Verilog.
Extensive architectural and verification knowledge of high performance bus protocols such as AHB and AXI.
In-depth knowledge in SoC architecture, including CPUs (preferably ARM), communications peripherals, multi-domain clocking, bus & interconnect structures, and power management.
Must have expert understanding of code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage.
Preferred Qualifications:
Knowledge of various networking protocols, microprocessor and CPU based designs, and Embedded software development experience is a plus
Knowledge in flow development and deployment of low power verification (including use of UPF and attaining comprehensive modal transition coverage) is a plus
Experience working on Gate Level Verification is preferred.
Education:
Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering and/or Electronics & Satellites Eng