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Wafersort Engineer
Ref No.: 18-13044
Location: Santa Clara, California
Start Date: 03/06/2018
Title: Wafersort Engineer
Location: Santa Clara, CA, United States
Duration ; long term

  
Job Description
 
·         Skill Set- Verigy93K, Advantest, Scan Chain, Digital BIST, Pattern conversion.
·         Multisite testing, Site to site correlation, Bench to Wafer correlation.
·         Class Test Wafer Test, Final Package Test & HVM statistical data analysis.
·         All IC's are High speed Analog IC's with limited digital interface. Engineering to HVM is expected for all IC's. Auto sort, multisite.
·         Statistical Yield Analysis of Sort data thorough understanding of Various Sort Testers like Advantest, Eagle, etc.. Shall be mastered in Advantest Verigy93K
·         Expertise in C++, automation scripting
·         Should have gone through full cycle of Wafer sort/Package sort from Engineering testing through Final HVM transfer
·         Expertise in using test equipment's like DSO, Sampling scopes, BERT, logic analyser, mustimeters, power supplies etc
·         PVT characterization @ wafersort