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ASIC/Digital Verification Engineer
Ref No.: 18-67607
Location: Santa Clara, California
Start Date: 09/14/2018
Job Title: ASIC/Digital Verification Engineer
Location: Santa Clara, CA


Job Description:


*Should have experience in DV IP & SoC Verification.

*Experience in developing Verification environments and BFM Integrations in SV & UVM.

- Responsible for Leading DV efforts at IP, Sub-system and SoC level.

- Interfacing with customer and owning the technical deliverable.

- Strong knowledge of digital design and SOC architecture, DSP/Modem CSI.

- Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM

- Analytical and Debugging skills



Primary Skills:

• Sample Skillsets: with 3 + to 10 years.

• UVM, C, DSP/modem background, Python scripting

• NOC Bus Fabrics, OCP, AXI bus protocols

• Low power DV with UPF.