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Analog IC design Engineer
Ref No.: 18-51959
Location: Chandler, Arizona
Position Type:Full Time/Contract
Start Date: 07/23/2018
 Analog IC design experience >14 yrs ; with at least 4 yrs of experience as Technical Lead
Experienced with analog blocks and subsystems from spec to GDS2; Lab Characterization of analog blocks will be an advantage.
Well versed and hands on experience on blocks such as Bandgap reference, LDO, LC VCO based PLL, DLL, Tx drivers(Voltage mode or current mode), Rx VGA amplifier, Linear equalizers, Decision Feedback Equalizers, Clock /Data recovery blocks including Interpolator.
Must have delivered at least one serdes block ( PLL block or Rx subsystem, or Tx subsystem) operating  at >1Gbps, as technical Lead
Having experience will process nodes below 28nm will be advantage. Must have understanding of processes from Layout perspective and must have ownership of the quality of Layout done by mask design team.
Must have used Cadence, Mentor and Ansys tools for design, and reliability verification