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Analog Layout Engineer
Ref No.: 18-51957
Location: Chandler, Arizona
Position Type:Full Time/Contract
Start Date: 07/23/2018
Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc.
· Should have worked on 14nm and below technology nodes on various analog mixed signal blocks such as PLL, Band gap, Client, DAC, SERDES, IO etc. and analog building blocks amplifiers, comparator, oscillator, voltage and current reference circuits etc.
· Good understanding of deep sub-micron and DFM issues and layout techniques
· Expert on Analog layout design of block level and chip level from schematics.
· Hands on experience in Analog Layout design of various designs
· Thorough working knowledge of layout design and verification tools
· Engineer should be well versed with Layout design tools.
· Engineer is required to work with circuit designers to meet design specifications.
· Ability to work with teams and juniors and guide them and sub delegate work, if required.
· Manage customer expectations and own deliveries as defined in the project schedule
· Excellent verbal and written communication