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DFT Engineer
Ref No.: 18-51083
Location: Santa Clara, California
Position Type:Full Time/Contract
Start Date: 07/19/2018
 
  • Overall 8+ Yrs of DTF Experience.
  • Expertise in Scan insertion, DFT Design Rules Check.
  • Expertise in ATPG. Debug and resolve ATPG DRC and chain trace issues. Coverage analysis experience.
  • Debug and resolve gate level pattern simulation issues, both no-timing and timing simulation.
  • Expertise in MBIST Planning/Insertion. Gate level simulations and debug.
  • Expertise  in JTAG and Boundary Scan.
  • Good Perl/tcl experience.
  • Good in communication.