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ASIC Design Verification Engineers
Ref No.: 18-49900
Location: san jose, California
Position Type:Contract
Start Date: 07/17/2018
 
As a MUST:
· Experienced in Verilog and OOPs
·Readily available
·Need people with hands on code experience
·Around the 3-6 year experience level ideal  
 
Spec : Must have: 
·         At least 3 years of hands-on relevant experience with pre-silicon verification
·         Must be a quick learner, independent and communicate well. Good logical and analytical skills.
·         Knowledge and hands on experience with Verilog, System Verilog
·         Must be proficient with :
o    OOPs
o    Classes, randomization, constraints, interfaces
o    building a testbench for a medium complexity block
o    writing & analyzing functional coverage, assertions
o    Generating and analyzing code coverage & writing waivers
o   Writing random tests, directed tests, error tests & performance tests for a block of medium complexity
o   Debug skills – able to isolate failures to environment, test or design.
 
Nice to have:
·         C++ knowledge and experience
·         Experience with verification of networking products (packet-based verification)