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Mask/Layout  Designer
Ref No.: 17-04132
Location: Hillsboro, Oregon
Position Type:Contract
Experience Level: 6 Years
Start Date / End Date: 03/27/2017 to 03/31/2018
Duration of assignment : Long Term
Industry:- Semiconductor

Mandatory skills :
1. 10nm / 14nm : Experience of working on 14nm/10nm Mask/layout design.
2. Experience in Genoa / Genesys ( Client Mask design flow), Helix
3. Worked on Analog / Mixed Signal designs.

Good to have:
· At least 4 – 8 years experience in understanding and Independent handling of various Analog and Mixed Signal blocks such as LDO/Voltage regulators, Switching Regulators, Data Converters, PLL, SerDes, LVDS and top level layout integration of AMS blocks.
· Good Understanding of deep sub-micron layout techniques issues in CMOS process technology nodes FinFET technology nodes ( 10nm/ 14nm, 16nm / 22nm)
· Experience in Genesys / Genoa layout editor, Aapr flow, Helix etc
· Good debugging skills in all physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC etc.
· Deep understanding of reliability analysis in layout like EM, IR drop, latch-up, ESD etc using Apache tools
· Should have good knowledge of CMOS, FinFET process and fabrication
· Proficiency in using industry standard EDA tools like Cadence (Virtuoso-L/Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC) , Hercules
· Knowledge of scripting languages such as Perl/Tcl and Skill is a plus.
· Full-chip integration and verification experience
· Good team player with excellent communication skills, interfacing with the circuit team

Job Responsibility:
- Layout design, Verification, Post-layout fixes and sign-off of high performance of Analog and Mixed Signal blocks, and IO / High Speed IO blocks
- Interface with the Circuit Design team at Onsite