ASIC Static timing analysis
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ASIC Static timing analysis
Ref No.: 18-31336
Location: San Jose, California
Position Type:Contract
Start Date: 05/07/2018
ASIC STA engineer responsible for the timing closure of a full chip SOC with 44 million gates and a max frequency of 1 GHz. Should have experience in STA for functional and DFT modes. Should have experience in Cadence STA tools- Tempus.
Should have experience in  noise analysis, early and late mode analysis, dc/AC scan mode timing analysis