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VLSI Physical Design Planning
Ref No.: 18-30810
Location: Folsom, California
Position Type:Contract
Start Date: 05/03/2018
 
·         VLSI Physical Design Planning-L2 (Mandatory)
·         Physical synthesis experience withplacement/routing studies for design optimization & convergence.
Complete floorplan including power domain planning, clocks and complete anysimulations needed to prove out line of sight to design convergence.
·         Experiencewith FinFet nodes - 14nm, 10nm
·         Should be able to lead a full chipof medium complexity up to 10 Mgates with a team or lead multiple blockimplementations or handled the critical task for a large hierarchical design(floorplan/PnR/STA etc for a 30 M gates design)
·         Ability to independently own all aspects of block level implementationsof large blocks 3-5M gates.
Perform Partition timing investigations and full-chip critical path analysis.
·         Synthesis run with initial UPF on latest RTL to get top-levelconnectivity analysis
·         Expertise with Synopsys tool suite (ICC2) is must. 
·         Enable PT based spec generation,  STA.