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FPGA design engineer
Ref No.: 18-30022
Location: San Jose, California
Position Type:Full Time/Contract
Start Date: 05/01/2018
Mandatory Technical Skills  Knowledge in C/C++, SystemVerilog, Python, IA, SoC Architecture, UPF, virtualizer and SIMICS Understanding of synthesis and timing analysis flow with involvement in at least one SoC design tape-out.
  • Must be with solid experience on system level debug involving multiple HW/SW/FW interaction.
  • Hands-on experience in RTL validation, SW validation, Power/Perf validation or manufacturing validation is a plus. Experience in Emulation, Virtual Platform, Altera/Xilinx/Synopsys/Mentor/Cadence Tools Flow, HAPS is a plus. Should have strong communication, analytical skill and a good team player.
  • PCIE verification
  • Memory Controller verification