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AMS Verification Lead
Ref No.: 18-26521
Location: Chandler, Arizona
Position Type:Full Time/Contract
Start Date: 04/17/2018
The candidate will design High Speed Interface Receiver circuits and component blocks.
As a Serializer/De-serializer (Serdes) receiver design engineer, you will be responsible for providing analog/mixed-signal solutions for transceiver IP in state of the art process technology.
Responsibilities Include
  • Conducting transistor-level feasibility studies for new circuit architectures.
  • Behavioral modeling of the receiver module to derive block-level requirements.
  • Defining bench-level test plans and validating, characterizing, and debugging designs.
Education Details
BSEE or MSEE, PhD preferred
Key Qualifications
Typically requires at least 7+ years of experience in analog mixed signal CMOS design.
Experience designing adaptive equalization, baseline wander and DFE circuit.
Knowledge of bandgaps, bias, opamps, LDOs, feedback, and compensation techniques.
Should be familiar with Cadence Virtuoso, Spectre, and/or C/Matlab/VerilogA modeling. Familiarity with various transceiver architectures and their trade-offs is considered a plus.