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Analog IC /Layout Engineer
Ref No.: 18-25243
Location: Chandler, Arizona
Position Type:Full Time/Contract
Start Date: 04/12/2018
As an RF PLL design engineer, you will be responsible for providing RF/analog/mixed-signal solutions.
Responsibilities Include
  • Designing various component blocks including PLL, VCO, LO generation, Dividers, Charge Pumps, XTAL, and other RF/mixed-signal blocks.
  • Conducting transistor-level feasibility studies for new RF circuit architectures.
  • Behavioral modeling of PLL to derive block-level requirements.
  • Defining bench-level test plans and validating, characterizing, and debugging designs through high volume production.
Education Details
BSEE or MSEE, PhD preferred
Key Qualifications
Typically requires at least 7+ years of experience in RF/analog CMOS design.
Experience designing fractional-N PLLs, sigma-delta PLLs, and VCOs.
Strong knowledge of loop design to optimize for phase noise/jitter, lock time, reference spur, area, power, etc.
Knowledge of bandgaps, bias, opamps, LDOs, feedback, and compensation techniques.
Should be familiar with Cadence Virtuoso, SpectreRF, and/or C/Matlab/VerilogA modeling. Familiarity with various RF transceiver architectures and their trade-offs is considered a plus.