Design Verification Engineer
Previous Job
Design Verification Engineer
Ref No.: 18-19407
Location: Santa Clara, California
Position Type:Contract
Start Date: 03/22/2018
  • Master's Degree in Electrical Engineering with 10+  years of Industry Experience
  • Experience in creating IP and Full Chip level verification plan and  test-benches from scratch  using Verilog/SystemVerilog/OVM/UVM
  • Experience in architecture and validation of CPUs, SOCs and industry standard IPs
  • Experience with development and usage of BFMs, transactors and protocol checkers used in simulation and HW emulation
  • Experience with scripting in Perl/tcl/shell to automate flows
  • Knowledge in IP and SOC development flows and methodologies
  • Proficient in all aspects of pre-silicon validation (functional, DFT, power, coverage, gate level)
  • Experience in delivering IPs or integrating IPs working with internal and external customers
Create validation plan using product/IP specifications/customer requirements and implementing the necessary verification environment