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Digital Design Engineer
Ref No.: 20-02664
Location: Menlo Park, California
Position: Digital Design Engineer
Location: Menlo Park, CA
Duration: Project through 6/2021 with possible extension to follow

Job Description:
We are looking for a Digital Design Engineer to implement custom logic in ASIC for our client's AR/VR products and in FPGA for prototyping and research. Areas of interests include Graphics, Audio or Compression. Primary language is SystemVerilog with some HLS where it is effective.

RESPONSIBILITIES
  • Implement and deliver verified RTL blocks given architecture and micro-architecture requirements.
  • Contribute to the architecture and micro-architecture requirements.
  • Support the DV, PD, and Firmware teams to ensure correctness of the delivered RTL.
  • Respond to issues found by engineers running the Lint, CDC, STA, Synthesis, and LEC tools.
  • Support handoff of RTL blocks to prototyping engineers for integrating the delivered RTL into FPGA platforms.

Requirements:
  • Experience in RTL coding. Preference for SystemVerilog.
  • Experience with the ASIC development flow from contributing to architecture, through owning micro-architecture and design, to assisting with first bring-up.
  • Experience solving Lint, CDC, STA, Synthesis, and LEC issues.
  • Experience with creating clear documentation and communications among and across the teams.