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Design Verification Engineer
Ref No.: 19-05422
Location: Menlo Park, California
Location: Menlo Park, CA
Duration: Through 9/2020
Company: A leader in the Social Media Networking company

We are looking for Design Engineer to Write and augment existing testplans.

· Write and augment existing testplans.
· Implement testbench and scoreboards / checkers.
· Implement test sequences as per plan and debug failures
· Achieve 100% functional and code coverage
· Work closely with designers, micro architects & f/w to resolve issues
· Ability to communicate & articulate clearly progress / issues with project leads

Required Skills:
5+ years of proven experience as a DV engineer
Hands on experience with SV and UVM
Hands on Experience with executable test plans and Coverage Driven verification
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Familiarity with C/C++

Desired Skills:
Python (or similar) scripting language
ASIC design experience
Experience in DSP based Audio or Computer Graphics or Compression' is desirable