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Verification Engineer III
Ref No.: 22-10188
Location: Remote Location, California
Pay Rate : $ 77.48 /Hour
Job Title: Verification Engineer (38574-1)
Location:  Remote/PST Hours
Job Type:  12 Month Contract *potential for extension
Pay Range: $70.00 to $76.00 per hour
*Access to Health Benefits + PTO

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Job Summary:
The main function of the Verification Engineer is to work with a group of engineers to drive end to end ownership of all verification tasks, ensuring that our client's IP, Subsystems and SoC's highest quality and reliability standards are met. In this role it is expected that the engineer will use strong collaboration skills across internal and external partners to identify, define and drive to closure all verification requirements. Additionally it is expected that the engineer should use their verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute test development, and drive coverage closure and reporting for the new product designs.

Job Responsibilities:
  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design, Firmware and Architecture teams
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Required Skills/Experience:
  • 7+ years experience working on IP/SS/SoC verification using UVM / SV based testbenches (must have)
  • 3+ years developing HW/SW co-design based tests (writing C code to run on internal MCUs in parallel with SV TB) (must have)
  • 3+ years GLS (Gate Level Simulations) experience (must have)
  • Enabling gate level simulations and power aware gate level simulations in a System Verilog testbench.
  • Extensive experience running GLS, GLS w/SDF, power aware GLS and debugging complex X-propagation and timing issues on interfaces
  • 3+ years working on externally sourced VIPs (eMMC, UART, SPMI, I2C/I3C, etc) (nice to have)
  • Experience owning an IP end to end (testplan creation, TB and test development, coverage closure) (nice to have)
  • Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation, Power Aware
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Bachelors degree in Electrical Engineering, Computer Science or equivalent experience