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System Validation Engineer
Ref No.: 20-03205
Location: Menlo Park, California
Tailored Management is seeking a candidate to join the world's largest social media network who enables over a billion users to openly connect with friends and family, share content, and explore the world. You'll have the opportunity to work with great people, tackle big challenges, and make a real impact – while being your unique, authentic, self at work!


System Validation Engineer
Menlo Park, CA
Health Benefits + PTO

Duration: Project through 7/30/21 with opportunity for extension/conversion based on performance!

This is a SOC ASIC target, but we are using a FPGA and Emulator, for silicon verification/validation. We need someone to contribute to the system verification - writing system-level tests running on the CPU and/or DSP which run on FPGA/Emulator. A mix of hardware and firmware/software background - since it's pre-silicon verification, writing FW like tests, for system level validation. 

Duties:
  • Writing CPP System Level tests targeting the CPU/DSP/CNN cores in CPP
  • Writing CPP Performance and Power system-level use-cases
  • Work on FPGA and Emulation scripts and flows for system validation, to increase productivity across the team
  • Work on post-silicon bringup and flows
  • Work closely with Algorithm engineers, DV engineers, Architects and Designers to come up with system level use-case scenarios
  • Work closely with Design Verification to enhance and augment verification for IPs on FPGA and/or Emulation platforms
  • Work closely with Firmware, Reference Modeling, and Software engineers to assist software development and debug
Job Requirements:
  • Experience in CPP for writing system level test-cases for SoC like IP
  • Experience in scripting languages such as Python, TCL etc
  • Experience running tests on FPGA and/or Emulation platforms for SoC like IP
  • Experience in post-silicon bringup and flows for SoC like IP
  • Experience with lab system debug with logic analyzers, scopes, meters, etc
  • Experience in performance evaluation and modeling for SoC like IP
  • Experience in power tests and evaluation on prototyping platforms
  • Familiarity with AMBA protocol, OCP protocol
  • Familiarity in System Verilog for design and verification - for debugging
Preferred Skills:
  • Performance modeling and evaluation
  • Knowledge of OS kernel and experience in driver development
  • Familiarity with IO’s such as MIPI CSI & DSI, USB, PCIE, LPDDR

Bachelor of Science required.

Languages: English( Speak, Read, Write )