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ASIC Design Verification Engineer
Ref No.: 19-06551
Location: Menlo Park, California
ASIC Design Verification Engineer
Location: Menlo Park, CA
Duration: Project through 9/2020 with opportunity for extension
Company: A leader in the Social Media Networking industry

System verilog coding of test-benches, to verify of ASIC and FPGA hardware blocks.
Work with designers for debug and coverage.
Help with ASIC verification infrastructure maintenance.
Help with Integration testing and regressions.
Assist with performance analysis, verification and improvement.

Required Skills:
Verilog / System verilog coding
Experience with one or more procedural coding languages (Python, C++)
Experience with UVM and / or modern ASIC Verification tool-sets.
System Verilog, UVM, ASIC Verification