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Design Aids and Automation Engineering Professional
Ref No.: 17-00209
Location: Essex Junction, Vermont
Position Type:Contract
Start Date: 07/10/2017
General Requirement: Design Aids and Automation Engineering Professional

Background: Be part of a dynamic and skilled IBM Research team developing test structure design enablement for the world's most advanced semiconductor technologies. Develop parameterized layout cells (pcells) and manual layout per specified requirements, using industry standard (EDA) tools including the Cadence Virtuoso Design Environment. Ensure that designed layouts pass Design Rule Checks (DRC). Specified layouts will be primarily test structures rather than working circuitry. Close and frequent cooperation with development engineers will be required.

Job Duties:
Job Duty 1 - Develop parameterized layout cells (pcells) per specified requirements, using industry standard (EDA) tools including the Cadence Virtuoso Design Environment.
Job Duty 2 - Interpret Design Rules and Macro Specifications. Work closely with process development engineers, test structure designers, and layout technicians to create layout automation that meets the intent of the test structure designers.
Job Duty 3 - Create manual layout per specified requirements, using industry standard (EDA) tools including the Cadence Virtuoso Design Environment.
Job Duty 4 - Debug and solve problems in a team environment.

Basic Skills, clearances and other elements required, in order of importance, and number of years experience, where applicable, in each skill:

Required:
1) Strong experience using the Cadence Virtuoso layout design tool, at least 3 years.
2) Experience with Cadence Skill programming language, at least 2 years.
3) Experience developing automation and scripting, at least 3 years.
4) Basic understanding of physical layout, technology groundrules, and semiconductor processing.
5) Ability to debug errors and solve problems.
6) Ability to work in a team environment.
7) Fluent English (both verbal and written) and strong communication skills.
8) Other: Preferred location is Essex Junction, Vermont. Alternate locations are Albany, NY; Hopewell Junction, NY

Other Skills Desired, Years in each skill, where applicable:
1) Preferred: Experience with advanced sub-micron semiconductor technology nodes.
2) Preferred: Experienced user of Calibre DRC checking tool.