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_Engineer: System Validation - III
Ref No.: 18-26812
Location: Folsom, California
System Validation Engineer III
We are looking for an enthusiastic engineer interested in working with Client's latest cutting-edge technology.
In this position, you will be part of the Functional Validation FV team in Folsom, specifically validating hardware features for Client PCH products. Creates, defines and develops system validation environment and test suites. Uses and applies emulation and platform-level tools and techniques to ensure performance to spec.
Responsible for the development of methodologies, execution of validation plans, and debug of failures.
Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on-die debug features. Self-motivation and problem solving are - Valued as you will need to understand silicon, board and software interactions

Qualifications required, not limited to the following:
Must have BS or MS in Electrical Engineering, Computer Engineering or Computer Science plus minimum of 6 year of experience with design or validation. At Master level, minimum of 4 year of experience with design or validation
Execution of validation test, triage and debug failure, verify and deploy fixes, Bring up platforms and test environment for Client products
Post Si validation
Silicon Debug
Experience with any PCH IP (USB, PCIe, Audio, Power Management)
Python
Systems engineering knowledge and Strong Computer Architecture knowledge. Minimum 4 year of post-Silicon validation or Silicon debug experience
Team player that can work in a high-paced, dynamic environment
A strong analytical mind with first-rate problem solving skills
Healthy paranoia for bugs and a strong sense of quality
Ability to work well in a cross-site cross-team environment
The CW will work in a fast paced environment with the PCH validation team in post si environment.
Desired Skills:
Understanding of USB, PCIe, Audio or Power Management feature would be a plus
Solid understanding of commercial OS would be an added advantage
Prior experience with Post Silicon debug tools, Scopes or LA would be a plus
JP#15989 and JP#15990 are the same sponsor
MRUNDA required